
module HalfWave_Rectifier
    #(
        parameter IWID = 12,
        parameter OWID = 32
    )
    (
        input wire signed [IWID-1:0] i_SigIn,
        input wire i_clk,
        input wire i_rst,
        output reg signed [OWID-1:0] o_result
    );

    reg signed [OWID-1:0] recto;

    always@(*) begin
        if(i_SigIn>=0) begin
            recto=i_SigIn;
        end
        else begin
            recto='b0;
        end
    end

    always@(posedge i_clk or posedge i_rst) begin
        if(i_rst) begin
            o_result<='b0;
        end
        else begin
            o_result<=recto;
        end
    end

endmodule
